Many of today's consumer electronic devices incorporate a significant number of integrated circuits in a very limited space. Significant pressure has been put on the integrated circuit packaging industry to incorporate the semiconductor die in exceedingly smaller packages. This industry pressure has lead to the development of the conventional quad flat packages (QFP). QFP's are formed with a semiconductor die connected to a lead frame and being encapsulated to form a package such that a plurality of leads extends laterally outwardly from each side of the periphery of the encapsulating structure.
Such a configuration is relatively simple in design and may be efficiently produced. However, the QFP-type semiconductor has shown various design and production limitations. For example, reducing the overall package size of a QFP becomes difficult because of the arrangement of leads about the lateral periphery of the package. This is particularly evident when reduced package size is attempted to be combined with increasing the number of input/output (I/O) connections required for the smaller yet ever-more complex dice representing the state of the art.
In order to increase the number of I/O connections while decreasing the package size a higher density of connections would be required along the package perimeter. However, such an increased density of leads about the package perimeter inherently requires a reduced pitch or spacing between adjacent leads and promotes an increased likelihood of cross-talk and signal interference as well as making such packages more difficult assemble in a high volume product.
In an effort to increase the number of connections in an integrated circuit (IC) package while decreasing the overall size, alternative packaging arrangements have been implemented. For example, grid array devices such as pin grid arrays (PGA), ball grid arrays (BGA), land grid arrays (LGA) and their associated variants have been used to reduce package size and increase input/output connections.
As an example of a grid array type device, a BGA device employs a number of input/output connections in the form of conductive bumps, such as solder balls, extending transversely from a major surface of the package in a pattern, or “array,” of columns and rows. The conductive bumps may be formed on one surface of a circuit board or other interposer substrate and are in electrical connection with bonding pads on the opposing surface of the circuit board. A semiconductor die is coupled to the bonding pads, such as by wire bonding, to establish electrical connections from the bond pads of the semiconductor die to the conductive bumps. The resulting assembly is then typically encapsulated such as by transfer molding with a filled polymer with the array of conductive bumps being left exposed for subsequent electrical connection to higher level packaging such as a carrier substrate.
The conductive bumps are configured to be coupled to a mirror image pattern of terminal pads on the carrier substrate which may comprise a printed circuit board (PCB) or another structure by reflowing the solder. In essence, a BGA device increases the number of input/output connections by allowing the connections to be positioned over substantially the entirety of a major surface of the package rather than extending laterally outwardly from the periphery of the package such as in a QFP.
While BGA and other grid array devices provide an increased number of input/output connections and may allow a simultaneous reduction in size for a given package, such devices are not without their own limitations and drawbacks. For example, the use of circuit board interposers, upon which the array of conductive elements is formed, imposes limitations on the size of the package since the circuit board is typically larger than the semiconductor die. Additionally, the circuit boards used in making BGA packages have been known to take on moisture during the fabrication process, leading to subsequent cracking and warping which cause early life failures of the device. Furthermore, the cost of circuit boards used in the fabrication of grid array type devices may also be viewed as a drawback.
Thus, a need still remains for leadless integrated circuit packaging system, which can resolve the manufacturing issues of the grid array devices while enabling the increased growth of input/output connections and shrinking size of the package outline. In view of the industry demand for higher levels of integration in smaller spaces, it is increasingly critical that answers be found to these problems. Also in view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to save costs, improve efficiencies and performance, and meet competitive pressures, adds an even greater urgency to the critical necessity for finding answers to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.